As achieving a high-integrated and high-performed LSI, miniaturization for a metal insulator semiconductor (MIS) type FET (hereinafter, simply called MISFET) has been advanced. Due to scaling down of a gate length by the miniaturization, so-called short-channel effect problem has significantly arisen in which a threshold voltage Vth is lowered. The short-channel effect is caused by influence of spread of depletion layers in source and drain regions of the MISFET to a channel region with a miniaturization of a channel length.
As a device structure capable of suppressing the short-channel effect, a FINFET has been paid attention in which a stripe-shaped (also referred to as fin-shaped) region (hereinafter, simply called fin) is formed on a silicon substrate, and a MISFET with a three-dimensional structure is formed in the region. In the FINFET, a fin inside is completely depleted by a potential applied to a gate electrode, and therefore, a good short-channel effect can be obtained.
For example, IEDM Technical Digest (2003), pp. 986 to 988 (Non-Patent Document 1) discloses a technique of controlling characteristics of the FINFET by a second gate (back gate) in which a potential in a channel region is electrically isolated from a first gate (front gate). In this manner, a different potential can be applied to the front and back gates provided on both side walls of the fin, respectively. And, a channel is formed on the one-side surface of the fin by the front gate, and a potential of the channel region is controlled by the back gate, so that a desired threshold voltage is obtained.
Also, for example, U.S. Pat. No. 7,629,651 (Patent Document 1) discloses a FIN-type FBC (floating body cell) memory arranged in array, which has front and back gates on side surfaces of a FIN-type semiconductor layer.
Further, for example, U.S. Pat. No. 7,355,253 (Patent Document 2) discloses a FinFET having first and second gates formed on side portions of a channel made of strained silicon.